1. Field of the Invention
The present invention generally relates to a data output circuit of a memory device, and more specifically, to a technology of generating a clock only when an output enable signal is generated to reduce current consumption.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a conventional data output circuit of a memory device. Here, a circuit having a burst length of 4 and a CAS latency of 6 is exemplified.
The conventional data output circuit of a memory device comprises a rising clock driving unit 2, a falling clock driving unit 4, an output enable signal generating unit 6 and an output driving unit 8.
The rising clock driving unit drives an internal rising DLL clock IRCKDLL generated from a Delay Locked Loop (hereinafter, abbreviated as “DLL”) to generate a rising DLL clock RCKDLL. The falling clock driving unit 4 drives an internal falling DLL clock IFCKDLL generated from the DLL to generate a falling DLL clock FCKDLL.
The output enable signal generating unit 6 generates a reference output enable signal OE00 in response to a read command RD, output enable signals OE10, OE20, OE30, OE40, OE50 and OE60 in response to the rising DLL clock RCKDLL, and output enable signals OE15, OE25, OE35, OE45 and OE55 in response to the falling DLL clock FCKDLL.
The output driving unit 8 drives data inputted synchronously with respect to the rising DLL clock RCKDLL and the falling DLL clock FCKDLL in response to enable signals OE00˜OE60 when the data are read, and outputs the driven data to an input/output pad DQ.
FIG. 2 is a timing diagram illustrating the operation of the data output circuit of FIG. 1.
The reference output enable signal OE00 is generated in response to the read command RD generated synchronously with respect to an external clock CLK inputted from a chip set.
Then, the output enable signals OE10˜OE60 are sequentially generated in response to the rising DLL clock RCKDLL before the external clock CLK.
Also, the output enable signals OE15˜OE55 are sequentially generated in response to the falling DLL clock CKDLL before a clock having an opposite phase to that of the external clock CLK.
Thereafter, first and third data DQ are outputted in response to the rising DLL clock RCKDLL (6.0 and 7.0), and second and fourth data DQ are outputted in response to the falling DLL clock FCKDLL (6.5 and 7.5).
The conventional data output circuit of a memory device, which includes a DLL, outputs the data DQ synchronously with respect to the rising DLL clock RCKDLL and the falling DLL clock FCKDLL. Here, the rising DLL clock RCKDLL is used in a replica delay block of the DLL, and the falling DLL clock FCKDLL is used only to output the corresponding data DQ. As a result, unnecessary operation current is consume when the corresponding data DQ are not outputted.